Technical Field
This invention is related to the field of integrated circuit implementation, and more particularly to the implementation of power management circuits.
Description of the Related Art
Computing systems may include one or more systems on a chip (SoC), which may integrate a number of different functions, such as, graphics processing, onto a single integrated circuit. With numerous functions included in a single integrated circuit, chip count may be kept low in mobile computing systems, such as tablets, for example, which may result in reduced assembly costs, and a smaller form factor for such mobile computing systems.
Each functional block included within an SoC may be designed in accordance to one of various design flows. The logical operation of some functional blocks may be described in a high-level computer language such as, e.g., Very-high-speed integrated circuit hardware description language (VHDL). Logic gate implementations of blocks described in such a fashion may be generated using logic synthesis and place-and-route design techniques. Other functional blocks, such as memories, phase-locked loops (PLLs), analog-to-digital converters (ADCs), may be designed in a full-custom fashion.
In some SoC designs, processors included in the SoC may enter an inactive state upon completing certain computing tasks to reduce power consumption or to reduce the emission of electromagnetic interference (EMI). Peripheral circuitry may similarly enter idle states to further conserve system power consumption or reduce EMI. In some designs, clock gating and power gating may be used to place functional blocks, such as e.g., processors, into inactive states. Clock gating entails disabling a clock from a functional logic block in order to reduce the amount of logic being clocked, thereby reducing switching power and reducing the amount of EMI being radiated. In a similar fashion, power gating involves a power source being disconnected from the functional block. Power gating may result in reduced switching power and leakage power. Clock gating may not reduce leakage power, but may reduce switching power of logic circuits within the SoC as well as the clock distribution network and may allow the logical state of the block to be maintained while the block is not being used.